Memory devices, such as dynamic random access memories (“DRAMs”), include one or more arrays of memory cells arranged in rows and columns. Each array may be divided into several sub-arrays. Typically, one or more digit or “bit” lines are provided for each column of the array, and each digit line is coupled to a respective sense amplifier. Each sense amplifier is generally a differential amplifier that compares the voltage at one of its inputs to the voltage at the other of its inputs. The sense amplifier then drives its inputs to complementary logic levels corresponding to the sensed differential voltage.
There are currently two array architectures that are commonly used in memory devices, such as DRAMs. In an “open” digit line architecture, the digit lines span two adjacent sub-arrays, and each digit line is coupled to each memory cell in a respective column. A sense amplifier is coupled to the digit lines of two adjacent sub-arrays. Thus, each sense amplifier is shared by two sub-arrays so that one input to the sense amplifier is coupled to the digit line of one array and the other input to the sense amplifier is coupled to the digit line of the other array. Prior to a memory read operation, the digit lines are precharged to a voltage that is typically one-half of an internal supply voltage, commonly referred to as DVC2.
In response to a memory read operation, one of the digit lines coupled to a sense amplifier is coupled to a memory cell being read. In response, the voltage on the digit line either increases or decreases from DVC2 depending upon the logic level stored in the memory cell. The other digit line remains at the precharge voltage, DVC2. The sense amplifier detects that the voltage on the digit line coupled to the memory cell being read has either increased or decreased relative to the precharge voltage and then drives the digit lines to complimentary logic levels corresponding to the sensed voltage.
The other architecture that is commonly used in memory device arrays is the “folded” digit line architecture. In a folded digit line architecture, each column is provided with a pair of complimentary digit lines, and the digit lines of each pair are generally coupled to alternate memory cells in the same sub-array. The complimentary digit lines are coupled to the inputs of a respective sense amplifier. Thus, the digit lines coupled to each sense amplifier are from the same sub-array.
A memory read operation in a folded digit line architecture is essentially the same as in an open digit line architecture. More specifically, the digit lines of each column are initially precharged to DVC2. In response to a memory read command, one of the digit lines coupled to the sense amplifier is coupled to a memory cell being read. In response, the voltage on the digit line either increases or decreases depending upon the logic level stored in the memory cell. The other digit line remains at the precharge voltage. The sense amplifier detects that the voltage on the digit line coupled to the memory cell being read has either increased or decreased relative to the precharge voltage. The sense amplifier then drives both digit lines to complementary logic levels corresponding to the sensed voltage.
Each of the above-described architectures has its advantages and disadvantages. A disadvantage of the open digit line architecture relative to the folded digit line architecture is that it is susceptible to errors resulting from noise because each sense amplifier input is coupled to a different array. In contrast, since both digit lines coupled to a sense amplifier in a folded digit line architecture extend closely adjacent each other through the same array, they tend to pick up the same noise signals. The differential operation of the sense amplifiers thus makes them insensitive to these common mode noise signals.
Although folded digit line architectures have better noise immunity, they have a significant disadvantage compared to open-array architectures in that they are less area efficient. Due to the nature of the layout of a folded architecture, each memory cell occupies 8F2 in area, where “F” is the minimum feature size of the semiconductor process. The layout of an open array architecture allows for a 6F2 cell area, thereby resulting in a 25% reduction over the 8F2 cell. Thus, open digit line architectures are theoretically substantially more area efficient than folded digit line architectures in using the surface area of a semiconductor die. Additionally, folded digit line architectures are susceptible to coupling with adjacent digit lines of the same array. As previously discussed, when a row of memory for an array is activated, all of the columns of memory cells are activated for that array. As a result, for a folded digit line architecture, coupling between the adjacent digit lines in the active array will result in higher currents and decreased sensitivity of the sense amplifiers.
In order to reduce digit line coupling in a folded digit line architecture, digit line pairs can be “twisted” at one or more places to reduce and balance the coupling to adjacent digit line pairs. The twisting improves the signal-to-noise characteristics. A variety of twisting schemes are used throughout the industry, as well known, resulting in each digit line pair is surrounded on two sides by other digit line pairs. Ideally, a twisting scheme will equalize the coupling terms from each digit line to all other digit lines. If done properly, the noise terms cancel, or at the very least, produce only common mode noise to which the differential sense amplifier is immune. However, each digit line twist region occupies valuable silicon area.
Therefore, there is a need for an alternative digit line architecture for use in memory devices.